This invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a method for manufacturing the gates of MOSFETs and the impurity profile of a diffusion layer formed with the gates used as a mask pattern.
The progress of the miniaturization technique in the semiconductor manufacturing process has enhanced the integration density of devices on one chip and maintained the high performance of the devices. When the above fact is taken into consideration, it becomes important to suppress a fluctuation in the performance of the devices in the process for a semiconductor device (LSI) which is an assembly of fine-patterned devices.
Cross sectional views of FIGS. 1A to 3 show a method for manufacturing a conventional semiconductor device. First, a p-type impurity diffusion region (p well) 2 and an n-type impurity diffusion region (n well) 3 used for forming nMOSFETs and pMOSFETs are formed in the surface area of a semiconductor substrate 1. Next, in order to electrically isolate elements from one another, a field oxide film (SiO.sub.2) 4 is formed by the selective oxidation method. Then, the impurity concentrations of the regions in the surface area of the semiconductor substrate are modified to adjust the threshold voltages (Vth) of the MOSFETs. The adjusting process is effected by implanting impurity ion from above a photoresist mask formed by the lithography process.
Next, a silicon oxide film 5 used as a gate insulating film is formed on the semiconductor substrate by the thermal oxidation method. A polysilicon film 6 is formed on the silicon oxide film 5 by the LPCVD (Low Pressure Chemical Vapour Deposition) method or the like.
Then, a gate electrode pattern is transferred onto a photoresist 7 by the lithography process (FIG. 1A). The polysilicon film 6 is selectively etched to form gates in a pattern corresponding to the mask pattern. For the etching process, anisotropic etching such as RIE (Reactive Ion Etching) having directivity and having a high selective etching ratio with respect to SiO.sub.2 is used.
After this, the resist is removed. In order to prevent the electric field from being concentrated on the gate edge portion, an oxide film 9 is formed to a thickness of approx. 10 nm around the gates 8 (FIG. 1B). Next, a photoresist pattern 10 is formed on the n well 3. Then, an ion-implantation process is effected with the photoresist pattern 10 and the gate 8 on the p well 2 used as a mask. As a result, n-type extension regions 11 of small film thickness are formed (FIG. 2A). The impurity profile in the depth direction of the extension region 11 steeply changes in the intermediate concentration range of approx. 5E18 to 1E20 cm.sup.-3.
Next, the photoresist pattern 10 is removed. Then, a photoresist pattern 10' is formed to cover the p well 2. Then, an ion-implantation process is effected with the photoresist pattern 10' and the gate 8 on the n well 3 used as a mask. As a result, extension regions 12 of small film thickness are formed (FIG. 2B). The impurity profile in the depth direction of the extension region 12 steeply changes in the intermediate concentration range of approx. 5E18 to 1E20 cm.sup.-3.
The extension regions 11, 12 are annealed at 1000.degree. C. for approx. 30 sec. and activated after the resist pattern is removed.
The impurity concentration of an LDD region of a MOSFET having a conventional LDD structure is lower than that of the extension region and is equal to or lower than 5E18 cm.sup.-3. The impurity concentration of the source/drain region of the MOSFET is generally approx. 1E20 cm.sup.-3 and corresponds to that of a high impurity concentration region. Therefore, if the impurity diffusion regions of the semiconductor substrate are defined according to the impurity concentration, the LDD region, extension region and source/drain region can be defined as a low concentration region, intermediate concentration region and high concentration region, respectively.
Next, Si.sub.3 N.sub.4 is deposited to a thickness of approx. 100 nm on the entire surface of the semiconductor substrate 1 by the LPCVD method. The deposited Si.sub.3 N.sub.4 layer is selectively etched in preference to the underlying oxide film (SiO.sub.2) film 9 by the anisotropic etching process such as RIE. As a result, side wall insulating films 13 are formed on the side walls of the gates 8.
Further, like the case of formation of the extension region, impurity regions 14, 15 of high impurity concentration (approx. 1E20 to 1E21 cm.sup.-3) are formed in the respective regions of the MOSFETs by the ion-implantation technique by using a resist pattern (not shown) formed by the lithography process and the gates as a mask and the impurity regions are annealed at 1000.degree. C. for approx. 30 sec. and activated. The impurity diffusion regions of the nMOSFET formed in the p well 2 are used as the n-type source/drain regions 14 and the impurity diffusion regions of the pMOSFET formed in the n well 3 are used as the p-type source/drain regions 15.
The extension regions 11, 12 are required to be formed shallow with a steeply changing impurity profile in order to suppress the short channel effect of the MOSFET, but since the source/drain regions 14, 15 are separated from the channel regions by a distance of the side wall length, they can be formed deeper with higher impurity concentration, thereby making it possible to reduce the sheet resistance of the source/drain region and realize highly operative MOSFETs. Further, the operation of doping impurity into the gate is effected at the same time that the n.sup.+ regions and p.sup.+ regions of the source/drain regions are formed. After this, an inter-level insulating film is formed by the LPCVD method and a wiring layer and the like are formed by use of a normal metallization process. Thus, a final semiconductor device (LSI) is completed.
FIGS. 4A, 4B show conventional gate electrode patterns. Gate pitches (intervals) in the semiconductor device (LSI) are set to various values. Even in a memory having the same pattern repeated many times in a simple form, the gate pitch is not uniform in the sense amplifier section and in the peripheral I/O section. Further, the non-uniformity of the gate pitch in the logic device is more significant.
The gate dimension of the MOSFET is one of the most important parameters for determining the performance of the semiconductor device (LSI). Enhancement of the performance of the LSI by miniaturization of the MOSFET is largely dependent on a reduction in the gate width (gate length).
It has become possible to form a fine pattern by reducing the wavelength of light used in the lithography and improving the photoresist material. However, the optical proximity effect and the loading effect of the photoresist occurring at the development/etching time cause an error in the gate dimension depending on the pitch or the like. The dimensional error of the gate lowers the manufacturing yield of the LSI and makes the margin design complex.
As a method for suppressing occurrence of the gate dimensional error, a method for designing a gate mask used for the lithography by repeatedly simulating the mask with the dimensional error taken into consideration is provided. However, it is necessary to take an influence by the two-dimensional process factor into consideration in order to correct the error, a long time is required for simulation in an LSI such as a logic device having various types of layouts, and some of the methods are not suitable for the actual mass production technique. In the simulation, the operation of modeling and recognizing variations in a gas, material and the like used in the process becomes necessary and it is difficult to promptly cope with the variations.
As shown in FIGS. 5A, 5B, pocket regions are formed under the extension regions in some cases in order to reduce the thickness of the extension regions and improve the short channel effect. Impurity of a conductivity type different from that of the extension region is ion-implanted into the pocket region. Therefore, the impurity concentration of the extension region steeply changes in the depth direction and the extension region is made thin and the punchthrough characteristic is improved.
The pocket region is an impurity diffusion region containing impurity of the same conductivity type as that of the semiconductor substrate and having an impurity concentration of 1E17 cm.sup.-3 or more which is higher than that of the semiconductor substrate. The pocket region is formed on the entire surface of the extension region.
Therefore, a large junction capacitance which cannot be neglected occurs in the boundary between the extension region and the pocket region, thereby degrading the operation performance.